The present invention relates generally to the use of partially defective memory chips or memory arrays. More particularly, the present invention relates to the use of a partially defective memory array to create a non-defective memory array.
As is well known in the art, during the production of monolithic memory devices from silicon wafers, memory storage cells can become defective and unreliable. These defective cells can be the result of a number of causes, such as impurities introduced in the process of manufacturing the monolithic memory device from the silicon wafer, or localized imperfections in the silicon substrate itself.
Often, while some memory cells in a particular memory array are defective, many other cells on the same memory array are not defective, and will work reliably and accurately. In addition, it is often the case that the defective cells are localized and confined to particular regions within the memory array. The remaining, non-defective regions, however, can be relied upon to provide a consistent and accurate representation of the information in the storage cell. What is needed, therefore, is a system or method for salvaging non-defective portions of memory arrays, even where the non-defective portions are not localized to any particular outputs on the memory module or memory array. Such a system preferably works transparently to the memory controller and is compatible with existing systems.
The present invention relates to techniques for salvaging non-defective portions of a memory array or memory module. In one embodiment of the present invention, the present invention relates to a method comprising the acts of: receiving an address from a processor; dividing the address into a row portion and a column portion; and modifying the address to preclude access to defective memory.
In another embodiment of the present invention, the present invention relates to a method of performing an operation on memory having defective memory cells comprising the acts of: receiving an address from a host bus; converting the address into a row address and a column address; and modifying the row address so that the defective cells in the memory are not addressed by the row address and the column address.
Additional embodiments and features, and the nature of the present invention may be more clearly understood by reference to the following detailed description of the invention, the appended claims, and to the several drawings herein: